Apple's A20 Pro Is the First 2nm Phone Chip. Its On-Device AI Claim Is Missing the Only Number That Settles It.

Apple announced the iPhone 18 Pro, the iPhone 18 Pro Max, and its first foldable, iPhone Duo, on September 9, 2026. Preorders open September 12; the Pro models ship September 18 at $1,199 and $1,299. iOS 27, carrying Siri AI, ships September 14.

This site does not cover phone launches. It covers the physical footprint of AI compute — power, wafers, packaging, heat — and it covers this one because the A20 Pro is the first leading-edge silicon of 2026 to reach volume, it consumed a large share of the industry's scarcest manufacturing capacity to get there, and Apple used its keynote to make a specific, checkable claim about running language models locally. That claim belongs to this beat. The camera does not.

What Apple actually confirmed

Apple's own figures, from its press release and product page, none of them independently verified on the date of publication:

The A20 Pro is built on a 2nm process. The CPU has six cores — two new performance cores Apple calls "super cores" and four efficiency cores — and, in Apple's words, "features integrated Neural Accelerators." The seven-core GPU is up to 40% faster than the A19 Pro's. The Neural Engine is now two 16-core engines, which Apple calls a Dual 16-core Neural Engine, 32 cores in total, for "double the AI processing power of A19 Pro." Memory bandwidth is up 50% over the A19 Pro. And Apple says the chip and a redesigned vapor chamber together deliver up to 40% better sustained performance than the iPhone 17 Pro.

Keynote coverage adds three figures that are not in the press release. MacRumors reported that the new neural accelerators deliver twice the FP8 performance of the previous generation, that the super cores are up to 20% faster, and that sustained performance is twice that of the A18 Pro. They may well be accurate transcriptions of the keynote, but Apple did not put them in writing.

The packaging is the detail that matters most. Apple says it is "inspired by M-series Apple silicon" and "places the silicon die side by side with the memory, removing the memory from the thermal path of the chip," which lets the die attach directly to a vapor chamber that Apple's product page says has three times the surface area.

Apple's framing was explicit: "the ultimate chip for running advanced on-device models."

The two specifications that are not marketing

Most of that list is ordinary generational improvement. Two items are not, and they are the two worth a reader's attention.

Memory bandwidth is the specification that bounds generation. A language model produces text one token at a time, and each token requires reading the model's active weights out of memory. On phone-class hardware that read, not the arithmetic, sets the speed. This site has measured it directly on Apple silicon: token generation is bandwidth-bound long before it is FLOP-bound, as the inference memory bandwidth runs show in detail. A 50% bandwidth increase is therefore closer to a direct statement about generation speed than any core count in the keynote. The reported FP8 gain points the same way: 8-bit floating point is the numeric format of H100-class accelerators, and it halves the bytes per weight against FP16. Fewer bytes per weight means more weights per second through the same memory interface. This site's quantisation tradeoff measurements cover what lower-precision formats actually cost in output quality on Apple silicon, which is the half of the story no keynote covers.

Leading with sustained performance is an admission. Apple quoted sustained performance, rebuilt the packaging to take memory out of the chip's heat path, and tripled the vapor chamber's surface area. Peak throughput sells benchmarks; sustained throughput is what a minutes-long generation actually experiences, and the gap between them is thermal. By putting sustained numbers in the headline and redesigning the thermal path to support them, Apple is conceding that the binding constraint on phone inference is heat rejection, not arithmetic.

That is the same constraint, at a different scale, that governs the buildings this site usually writes about. It is also what this site's own sustained throughput runs on an M1 found: local inference on Apple silicon is a thermally limited workload long before it is a compute-limited one. The A20 Pro's most interesting engineering is a cooling story.

How Apple's AI stack is built, layer by layer

A chip is only half of an on-device AI claim. The other half is the models and software that decide what the chip is asked to do. Apple published most of that stack at WWDC in June, in its machine learning research and security documents, and the A20 Pro is the first chip designed with the third generation of it already public. Read from the bottom up, there are five layers.

Layer 1 — compute blocks. The A20 Pro has three places where AI math can run: the CPU with its integrated Neural Accelerators, the seven-core GPU, and the Dual 16-core Neural Engine, which Apple says "accelerates on-device AI models and computational photography." Apple does not publish which block runs which model, or how work is split between them, and this post does not guess.

Layer 2 — memory and storage. The compute blocks share one pool of unified memory, and its bandwidth is what rose 50%. Beneath it sits flash storage, which is now part of the AI stack rather than just a place to keep photos. That is the layer the model design below depends on.

Layer 3 — the models. Apple's third-generation foundation models, AFM 3, are a family of five that Apple says were "custom-built in collaboration with Google." A January joint statement put it more plainly: the next generation of Apple Foundation Models "will be based on Google's Gemini models and cloud technology." Two of the five run on the device:

• AFM 3 Core, "the next generation of our 3-billion-parameter dense model," the general-purpose on-device model.
• AFM 3 Core Advanced, which Apple calls "our most powerful on-device model": a 20-billion-parameter sparse model "activating just 1 to 4 billion parameters at a time depending on the request." Apple says it is "unlocked by and optimized for our most capable Apple silicon systems."

The other three — AFM 3 Cloud, ADM 3 Cloud for images, and AFM 3 Cloud Pro — run on servers.

Layer 4 — the frameworks. Developers do not program the Neural Engine directly. Apple's June developer announcement describes three routes in. The Foundation Models framework is "a single native Swift API" that reaches both the on-device models and the server models. Core AI, which is new this year, is "optimized for the unified memory and Neural Engine of Apple silicon, allowing developers to deploy full-scale LLMs locally" — models a developer brings, rather than Apple's. And App Intents is how an app exposes its actions and content to Siri AI.

Layer 5 — the features. Siri AI, Writing Tools, Visual Intelligence, and photo editing are what the user actually sees. Apple says Siri AI "can draw on personal context understanding to search across messages, emails, photos, and more," can answer questions about what is on screen, and can "get things done across apps" — the last of which only works because apps have described themselves through Layer 4.

Beside the stack — Private Cloud Compute. Requests the device cannot handle go to Apple's server tier. As first designed in 2024, it ran on "custom-built server hardware that brings the power and security of Apple silicon to the data center," with the Secure Enclave and Secure Boot from the iPhone. A device encrypts its request only to servers whose attested software appears in a public, append-only transparency log, and those servers are required to keep no user data after they respond. In June Apple extended the system beyond its own hardware: "For AFM 3 Cloud Pro, we worked with Google and NVIDIA to extend Private Cloud Compute to NVIDIA GPUs in Google Cloud," using NVIDIA Confidential Computing, Intel CPUs with TDX, and Google's Titan chip. Apple says its "core PCC requirements remain exactly the same."

Where the hardware and the software meet

The layers are not independent. Three places in Apple's own documents show hardware limits shaping software design, and the reverse.

Flash storage shaped the model's architecture. A 20-billion-parameter model is too large to keep in a phone's working memory at once. Apple's answer is to not try: "the full model is stored in flash memory (NAND)," and only the parts needed are moved into DRAM. The interesting line is the next one. Standard mixture-of-experts models pick different experts for every token, but "because NAND-to-DRAM bandwidth is too slow to swap weights token by token, as standard MoE models require, AFM 3 Core Advanced makes routing decisions per prompt." A lightweight dense block chooses a fixed set of experts at the start and occasionally reselects them, and a high share of "shared experts" stays in memory permanently. The speed of the storage chip decided how the model thinks. That is hardware–software co-design stated in one sentence, and it is the clearest reason Apple can say its best model is "unlocked by" specific silicon rather than simply faster on it.

Memory bandwidth decides how fast the active slice runs. Once the chosen experts are in DRAM, generation behaves like any small dense model: each token reads the active weights, somewhere between 1 and 4 billion parameters according to Apple. That is exactly the workload where bandwidth, not compute, sets the pace. It is an inference, not an Apple statement, that the 50% bandwidth increase and the sparse model were designed with each other in mind. But the two fit together too neatly to be a coincidence.

The device list is where hardware becomes a software feature. Siri AI runs on devices back to the iPhone 15 Pro, according to Apple. Engadget reported that iPhone 17-generation devices and later get "a more powerful on-device model," consistent with Apple's statement that Core Advanced is limited to its "most capable Apple silicon systems." Apple has not published the exact list or the RAM each device needs, and this post will not repeat the leaked one. The pattern is the point: the model family is sized to the silicon, and the silicon is what decides which features a given phone gets.

What these three points add up to for this site's beat is simple. Apple has spread one AI system across three physical places: the phone's battery, Apple-silicon servers, and, since June, NVIDIA GPUs in Google Cloud. Each has its own power contract, its own cooling, and its own supply chain. The A20 Pro moves more of that work onto the first of the three. It does not tell you how much, and that brings us back to the missing number.

The wafers this chip came out of

Leading-edge wafer capacity is the tightest input in the compute supply chain, and it is not segmented by end market. DigiTimes reported in August 2025 that Apple had ordered almost half of TSMC's initial 2nm capacity for the iPhone 18 generation, against an N2 ramp of roughly 45,000-50,000 wafers per month at the end of 2025 scaling past 100,000 per month during 2026.

That figure deserves care. It is single-sourced trade-press reporting from over a year ago, it describes initial capacity rather than the current or full-year split, and neither Apple nor TSMC has confirmed it. Treat it as directionally informative, not as a settled number — the same standard this site applied to the analyst wafer estimates in its CoWoS packaging bottleneck coverage, where TSMC's CEO named the constraint on the record but the company declined to attach wafer figures to it.

With that caveat, the structural point holds and is not seriously disputed: a very large fraction of the first 2nm output went into consumer devices. Every wafer that becomes an A20 Pro is a wafer that did not become something else, in a year when TSMC's own leadership has said capacity is limiting its customers' growth. The AI buildout and the iPhone are competing for the same physical output of the same small number of fabs — a dependency this site has traced before in Sovereign Compute, Splintered Silicon.

The useful inversion: a consumer product cycle is now a variable in AI infrastructure supply. Not a metaphor for one.

Innovation, increment, and experiment

Sorting the launch on engineering grounds rather than launch-day enthusiasm.

Structural — the 2nm node and the thermal path. A full node transition plus packaging that takes memory out of the heat path and attaches the die directly to a larger vapor chamber changes the performance envelope rather than the feature list, and it is the part competitors cannot answer inside a product cycle. The sustained-performance figures are the claim to test.

Structural — memory bandwidth and the flash-resident model. A 50% bandwidth increase, paired with a 20-billion-parameter model that streams its experts from flash, is the combination that decides whether a large local model runs usefully or merely runs. Neither half makes sense without the other.

Increment — variable aperture, the smaller Dynamic Island, the C2 modem. Real engineering, genuinely useful, and none of it changes what the device is capable of in kind. The C2 modem matters commercially, as continued substitution away from a purchased component, and Apple says it uses 15% less energy than the C1X, but that is a supply-chain and efficiency fact rather than a new capability.

Experiment — iPhone Duo, at two thousand dollars. Announced September 9, reported by MacRumors as starting at $2,000 and not launching until October at the earliest. A constrained first-generation form factor at that price is a market test, and should be read as one.

Experiment — Apple Reference Image. A provenance signal for verifying a photograph is not AI-generated. Interesting, and unproven: provenance systems fail on adoption and adversarial pressure, not on the quality of the initial implementation.

The number nobody published

Here is the gap this post exists to name.

Apple made a claim about running language models on the device. To evaluate it, you need to know what a token costs in joules. Not compute delivered, not a ratio against last year's chip — energy per token. That number decides the entire question the on-device AI pitch rests on, because "runs locally" is not the same as "costs less." Local inference does not make the energy disappear. It moves it from a data center's power contract to a battery the user recharges, and whether that trade is favourable is an empirical question with a real answer.

The stack makes the question harder, not easier. A single Siri AI request may run entirely on the phone, on Apple-silicon servers, or on NVIDIA GPUs in Google Cloud, and Apple does not say which. Flash-resident models add a cost that the tokens-per-second figure does not capture: moving experts from NAND into DRAM at the start of a prompt takes energy that is spent before the first token appears.

Nobody published energy per token yesterday. Apple did not, and phone reviewers will not, and the reason is not that anyone is hiding something.

This site tried to measure exactly that quantity on Apple silicon and failed, in ways it published in full. The macOS battery gauge holds each value for 51-59 seconds while the generations being measured last 2.8 to 5.4 seconds. Where a window long enough to beat that refresh rate existed, two independent derivations of the same energy — integrating instantaneous power, and reading the battery pack's own coulomb counter — disagreed by 2.05x over the same 21-minute run. The analysis script emitted a marginal energy figure of exactly 0.00 J/token for two models, which reads like a clean result and is actually an instrument that never resolved the load.

That was on a Mac, with a shell, with unprivileged access to power telemetry that iOS does not expose at all. If per-query energy is not measurable on an M1 without root, it is not going to be measured on an iPhone by a reviewer with a stopwatch and a battery percentage.

So the honest position on September 10, 2026 is this: Apple has shipped hardware that is very likely much better at local inference, on specifications that are the right specifications to care about, paired with a model architecture visibly designed around that hardware's limits. The claim that this makes AI cheaper or greener is unevidenced in both directions. This site's local versus cloud crossover work covers where that boundary sits on measurable axes — latency, throughput, cost — and energy is precisely the axis that stayed out of reach.

What would settle it

Four things, in rough order of tractability:

A tokens-per-second figure for a named model at a named quantisation on retail A20 Pro hardware, sustained over a run long enough to reach thermal equilibrium rather than a first-30-seconds burst. Any competent reviewer with a shipping device can produce this after September 18, and it would be the first real datapoint about the chip's inference behaviour. Developers using Core AI to run their own models will be able to publish it too.

A power figure taken at the wall during that sustained run — charge the device from empty at a known state while looping generation, and difference against an idle baseline. Crude, and far better than nothing, because it sidesteps the on-device telemetry that made the M1 measurement fail.

A statement from Apple of where Siri AI requests run: which features stay on the device and which go to Private Cloud Compute or Google Cloud. Without it, no energy comparison between on-device and cloud AI on an iPhone can be done honestly, because nobody outside Apple knows which side a request is on.

Disclosure from Apple of a wattage envelope for the Neural Engine under sustained load. Unlikely, and it is the number that would end the argument.

Until one of those exists, "the ultimate chip for running advanced on-device models" is a statement about compute delivered per second. It is not a statement about what the compute costs, and the two are routinely confused — including, frequently, by people who know better.

Sources

• Apple's iPhone 18 Pro press release and product page, September 9, 2026 — every A20 Pro figure attributed to Apple in this post, and the source the correction follows; none of it is independently verified
• Apple Machine Learning Research and Apple Security Research, June 2024 and June 2026 — the AFM 3 model family, the flash-resident design of AFM 3 Core Advanced, and Private Cloud Compute's original design and extension to NVIDIA GPUs in Google Cloud
• Apple Newsroom, June 8, 2026 — the Foundation Models, Core AI, and App Intents frameworks; and the Google–Apple joint statement of January 12, 2026 on the Gemini collaboration
• MacRumors, 9to5Mac, and Engadget, September 9, 2026 — keynote-only figures (FP8, CPU speed, the A18 Pro comparison), configuration and dates, and the iOS 27 release and device-support reporting, each labeled as such
• DigiTimes via MacRumors, August 28, 2025 — the "almost half of initial 2nm capacity" allocation claim and the N2 wafer ramp figures, labeled throughout as single-sourced trade-press reporting that neither Apple nor TSMC has confirmed
• This site's own committed measurement data — data/energy-per-token/ for the failed per-query energy measurement and its 2.05x reconciliation failure, and the sustained-throughput and memory-bandwidth run logs cited via the linked posts

No figure in this post describes measured A20 Pro silicon, because none exists yet. Apple's claims are labeled as Apple's claims, keynote-only figures and trade-press reporting are labeled as such, and the first-hand measurements are this site's own and are about a different chip.