TSMC's Earnings Call Reveals the Real AI Chip Bottleneck: Not the Fab, the Packaging

This site has covered TSMC's foundry market-share dominance and its geopolitics before, in Sovereign Compute, Splintered Silicon — that post is about who controls wafer fabrication. This one is about a narrower, different constraint that TSMC's own CEO named directly on the company's July 16, 2026 Q2 earnings call: not the fab, the packaging.

What TSMC's CEO actually said

Most coverage of AI chip supply focuses on wafer fab capacity — how many 3nm or 2nm wafers TSMC can produce. On the earnings call itself, CEO C.C. Wei said something more specific and, for anyone tracking AI hardware supply, more useful: "Our packaging capacity is so tight that now it's limiting my customers' growth." That's CoWoS (Chip-on-Wafer-on-Substrate) — the advanced packaging process that binds a GPU or AI accelerator die to its HBM memory stacks — not the front-end wafer fabrication most reporting treats as the bottleneck. Wei followed that admission with something almost as telling: he said TSMC "welcome[s]" competitors offering packaging alternatives, because "that will help TSMC's front-end wafer business growth" — the company's own wafer-fab business is constrained by a packaging step it doesn't fully control the pace of, and it's openly fine with rivals absorbing some of that overflow.

TSMC did not put a wafer-per-month number on the record for CoWoS capacity — that's worth stating plainly rather than blending analyst estimates into the company's own disclosures. What's reported, consistently across TrendForce and several other trade-press estimates: CoWoS capacity around 13,000 wafers/month at the end of 2023, roughly 35,000 by end-2024, about 75,000 by end-2025, and a targeted 125,000-130,000 by the end of 2026 — close to a 4x expansion in three years. TrendForce separately reported the CoWoS supply-demand gap narrowing from roughly 20% to about 10% by end-2026. Those are real, widely-corroborated estimates, but they're estimates, not TSMC's own confirmed figures — the CEO's "so tight it's limiting my customers' growth" is the one first-party data point in this section.

The guidance raise that goes with the admission

TSMC's own numbers, not estimates: CFO Wendell Huang confirmed the company "decided to raise our full year 2026 capital budget to be between $60 billion and $64 billion" — up from the $52-56 billion range TSMC gave in January 2026. Wei separately confirmed full-year 2026 revenue growth guidance moved to "slightly above 40% year-over-year in U.S. dollar terms."

A capex raise mid-year, on top of an already-large original budget, is a company putting real money behind the constraint its own CEO just named in public. Wei also pointed to a specific demand driver behind the packaging squeeze that gets less coverage than GPU demand itself: "The emergence of agentic AI is leading to a resurgence in the role of CPUs in AI data centers, which drive more silicon demand" — a second silicon-demand vector, not just accelerator chips, adding to the same packaging queue.

What this doesn't settle

TSMC's own 2nm (N2) node contributed 3% of Q2 wafer revenue and is expected to dilute gross margin by 3-4 percentage points during its ramp — Huang's own figures, not estimates — which is a separate, ordinary new-node cost story, not the packaging bottleneck. And a packaging bottleneck easing toward 2026-2028, even at TSMC's own stated pace, doesn't mean the AI chip supply chain as a whole loosens on the same timeline: this site's HBM memory supercycle reporting covers a separate, not-yet-resolved constraint on the memory stacks CoWoS is packaging chips together with. A GPU needs both an available packaging slot and available HBM at the same time — easing one queue doesn't clear the other.

Sources

• TSM (TSMC) Q2 2026 earnings call transcript, July 16, 2026, via The Motley Fool — C.C. Wei and Wendell Huang direct quotes on packaging capacity, guidance, and N2 ramp
• TSMC's own January 2026 (Q4 2025 call) capex guidance of $52-56 billion, reported via TrendForce and Data Center Dynamics
• TrendForce, "TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026" (June 2026) — CoWoS wafer-capacity trajectory estimates, explicitly labeled as reported/estimated in this post, not TSMC-confirmed
• This site's own Sovereign Compute, Splintered Silicon and HBM Memory Supercycle — cited for related, separately-sourced context, not re-derived here

All figures independently cross-checked across at least two sources before publication. Every number described as TSMC's "own" in this post is a direct quote or disclosed figure from the earnings call transcript itself; every wafer-capacity figure is explicitly marked as a reported analyst estimate.